CPU體積面積有可能做大嗎 - 3C
By Hardy
at 2019-12-26T22:35
at 2019-12-26T22:35
Table of Contents
推文有幾個有趣的點可以回覆一下
→ arrenwu : 問題是...有哪間fab願意做這種呢? 12/26 18:34
輪班星跟神教
噓 AXby : 你先教我怎麼曝 12/26 18:35
進得來我就教你啊
用Canon的曝光機就做得到,還不用動到ASML
當神教每個人都塑膠?
→ arrenwu : 問題是這種晶片良率應該很難看 12/26 18:37
你錯了,這良率一定是100%
因為它在12吋wafer上只能塞一顆die
如果這顆死掉了,神教就準備賠錢
至於會用什麼暗黑兵法讓它100%良率出去
推 doledo01 : 好像說晶圓尺寸不再做大 往製程發展 12/26 19:18
1. 不要小看warpage,它某種程度是比gate length還可怕的物理天險
未來可能會出現新材料做到0.1nm工藝,但wafer應該還是會停在12吋
2. wafer做太大,人會不好拿......
半導體工廠不可能什麼地方都有Robot跟天車幫忙送貨
上面講神教在玩的就這個
基本上就是當練手的啦 不可能靠這個賺錢
明年神教要賺多少要看聯fuck跟***的5G modem
我們還怕還沒驗證完 這間公司就倒了勒
玩了一輪結果收不到錢 慘
推 lin793156 : 做大幹嘛啊,就放多一點核不就好 12/26 20:59
不做大其實就是成本考量而已
否則不顧成本下去做,活著出來的成品是可以很恐怖的
Cerebras那片上面整合幾十種module
module彼此近到之間什麼程度? 光是直接在module之間打in-die wirebond
訊號延遲都可以屌虐目前最強的MCM封裝
還不用玩到2.5D勒
--
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